Recently there was a couple questions posted on the TCAD Professionals thread at LinkedIn from a user named Bejoy. While Bejoy asked specifically about Silvaco software, the discussion really applies to many tcad software packages.
Question 1: In a 2D simulation, do we have to place the thermal contact on the bottom of the device or anywhere on the x-y structure.
Answer 1: The ideal location depends on what you are trying to achieve with the simulation. The thermal contact sets a boundary condition and it’s placement and other characteristics can drastically affect your results. That you say it didn’t affect anything is a bit worrisome, you should carefully examine your simulation to determine why. It may be reasonable, or not, depends on exactly what you did. Also what you are trying to simulate may or may not place it close to the maximum dissipated power area.
Usually one tries to simulate a situation that occurs in real life, particularly the measurement you will correlate to. Unfortunately we are not always able to simulate that exact situation and one is forced to create an approximate equivalent.
If your simulating the measurement setup this often means building some substrate into the simulation and putting the thermal BC on the “chuck”. Your sidewall boundary conditions ought to be infinite since more than likely it’s a test chip with one DUT. If the device simulation is of one device in an array, or part of a device, then reflecting boundary conditions may be more appropriate for the sidewalls.
One free adjusting variable in much of this is often the thermal resistance. You will be lucky if you have data on what it really is for your real world setup. Even if you do, it’s likely you need to change it since chances are you will need to use an equivalent setup, and the thermal resistance will need to be adjusted to account for the differences.
An example that illustrates this is simulating a device in a plastic package. You probably can’t simulate the whole device, let alone the whole package. The only real thermal resistance you might know is the outside of the package. The plastic to die interfaces get one treatment, and the device sidewalls would normally be reflecting or infinite.
It’s not pretty and it’s not simple, you really need to think through what you are trying to simulate and plan appropriately. You might even need to bring in an FEA tool like Ansys to do the large scale simulation and marry the results to your TCAD setup, it’s been done and works.
Question 2: I am trying to simulate a MOSFET cell. Since a MOSFET consists of millions of cells, I am not sure if we can simulate the entire device. I wonder how device manufacturers do it when they publish the results in a datasheet?
Answer 2: For a power MOSFET you would simulate a single cell, or 2D X section of the cell. You would want the sidewall BC to be reflecting (since as much heat would be flowing in from adjacent cells as would be flowing out of the simulated one). you would scale the results to your entire device.
For datasheets it is not necessary to do an actual measurement, nor do you need to use TCAD device simulators*. Extremely good results (<10%) are easily and reliably obtained using a tool such as Ansys. For this you need to know details about the package, the wattage being dissipated in your device, and the standard test setup being used to generate the datasheet numbers. (For an example see “Thermal Numerical Simulation and Correlation for a Power Package”, Electronic Packaging Technology, 2007. ICEPT 2007. 8th International Conference, Aug. 2007 Page(s):1 – 5
* If you don’t know the wattage a new MOSFET will dissipate, you could use the TCAD device simulator to get the IV curve.
In theory one should be able to do the entire simulation in a TCAD simulator. Reality is that for a MOSFET with millions of cells the computational requirements would be so large as to make this impractical, the ability of any existing codes to actually do this is dubious, and it is much more efficient to use other methods.